This invention generally relates to wafer electrical testing methods and more particularly to an improved method for providing rerouting electric signal connection pathways to provide for an improved signal rerouting methodology during wafer electrical testing (WET).
Since the introduction of semiconductor devices, the size of semiconductor devices has been continuously shrinking, resulting in smaller semiconductor chip size and increased device density. One of the limiting factors in the continuing evolution toward smaller device size and higher density has been the increased difficulty of forming high aspect ratio electrical interconnects with sufficient electrical reliability. Wafer inspection and testing methods are typically performed following the formation of various levels in a multi-level device, however many electrical connection defects are frequently missed or are not exhibited until final wafer electrical testing (WET) which is performed to check the electrical functionality of the semiconductor device as a whole as formed on individual wafer die prior to sawing or dicing the wafer into individual die.
For example, in a multi-level semiconductor device there are frequently formed metallization layers that include relatively wide metal areas, for example greater than about 1 micron which are connected to other metallization layers, either overlying or underlying through relatively narrow metal filled holes, also referred to as vias. Frequently, several vias will connect one or more metal interconnect lines in one metallization level to an overlying metallization level including a relatively wide metal area through several vias. The electrical continuity of the various metal interconnects, particularly through the vias is critical to proper functionality of a device.
Copper and copper alloys are increasingly becoming the metallization metal of choice as it has improved electrical resistivity and resistance to electrical migration compared to aluminum, a previously widely used metallization metal. The use of copper, however, has presented several technical manufacturing problems that must be overcome for successful implementation of the technology. For example, copper cannot be successfully etched to form metal lines since it does not form volatile components with known etching chemistries. As a result, copper lines must be formed as metal inlaid structures, also referred to a damascenes or dual damascenes where an anisotropically etched opening is formed in a dielectric insulating layer followed by filling the opening with copper and planarizing the wafer process surface by a chemical mechanical polishing step.
The copper is increasingly deposited according to an electro-chemical deposition process after depositing a copper seed layer according to a PVD or CVD process to provide an electrode surface for copper deposition. In addition, a barrier/adhesion layer is typically deposited to line the anisotropically etched opening prior to copper deposition to prevent the diffusion of copper through silicon oxide based dielectric insulating layers. Following copper deposition, a chemical mechanical polish (CMP) process is performed to remove excess copper and planarize the process surface in preparation for the formation of overlying layers.
Several problems with copper semiconductor processing technology may act to cause open electrical signal pathways to occur, particularly in relatively narrow vias that electrically connect metallization layers. For example, with respect to relatively wide metal areas, for example greater than about 1 micron, CMP processes tend to preferentially cause dishing of the copper area where it is slightly depressed with respect to the plane of a surrounding oxide area. As a result, subsequent formation of an overlying via may result in an open electrical signal pathway. Other problems affecting via interconnections are believed to be related to galvanic erosion effects during the CMP process where a partially exposed barrier/adhesion barrier layer at the process surface forms in the presence of copper a galvanic cell leading to preferential erosion of the copper area with the similar result that a via formed overlying the eroded or depressed area may result in an open electrical signal pathway. Yet another phenomenon believed to cause electrically open pathways is related to exposing the copper to high temperatures during subsequent processing steps which may lead to the formation of copper protrusions at copper surface areas underlying via formation, which through subsequent thermal expansion and contraction of the copper, may lead to a discontinuous electrical signal pathway to the overlying via.
For example, referring to FIG. 1A is shown the relationship of metallization layers in a multi-level (layer) semiconductor device showing only the metallization layer portions for simplicity. For example the multi-level device includes for example Mn metallization layer 12 including relatively wide metal line 18A electrically connected to a relatively narrow metal line 18B. Metallization layer 14 e.g., overlying. metallization layer Mn+1 includes metal lines e.g. 16A, 16B, and 16C electrically connected to metal line 18A through metal filled vias, for example copper vias, 17A, 17B, and 17C, respectively. Referring to FIG. 1B is shown a view of a cross section indicated by line A through metal line 16C shown in FIG. 1A. Shown on the surface of metal line 18A, for example copper metal line in metallization layer 12, is humped portion 18C underlying via 17C, for example a copper filled via, the hump being attributed, for example, to a manufacturing process defect in forming copper line 18A. The humped portion 18C may lead to an electrically open signal pathway, for example following subsequent manufacturing processes causing thermal expansion and contraction.
According to the prior art, during WET testing, electrical signals are passed through the various electrical interconnects by means of an automated probe system which sequentially applies an electrical signal to various parts of the wafer surface in an effort to determine the electrical signal pathway integrity of the semiconductor device and provide for signal routing maps for subsequent wiring and packaging processes.
One problem according to the prior art is that there are a limited number of metal lines or electrical signal pathways within the device through which a signal may be passed, also referred to as routing resources. A problem with prior art WET methods is that frequently, in the event one or more via electrical connection pathways fail or open, is the limited ability to reroute an electrical signal due to limited routing resources.
For example, referring to FIG. 1A, in the event via connection 17B fails due to an electrical open, rerouting of the electrical signal pathway through metal line 16B to wide metal line 18A would be impractical with the routing resources shown, requiring the use of other scarce routing sources not shown.
There is therefore a need in the semiconductor manufacturing art to develop an improved method for wafer electrical signal rerouting including wafer electrical testing such that routing resources are increased to provide for improved rerouting options for more improved electrical testing and operation of a semiconductor device.
It is therefore an object of the invention to provide an improved method for wafer electrical signal rerouting including wafer electrical testing such that routing resources are increased to provide for improved rerouting options for more improved electrical testing and operation of a semiconductor device while overcoming other shortcomings of the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for selectively providing and utilizing electrical pathway routing resources in a semiconductor device.
In a first embodiment, the method includes providing a multi-level semiconductor device including at least two metallization layers having respective metal lines for carrying electrical signals. The metal lines including first metal lines provided for electrical communication with a third metal line where the first metal lines and third metal line are provided in a common metallization layer and second metal lines are provided for electrical communication with the third metal line through respective vias. The second metal lines and third metal line are provided in respective separate metallization layers where at least one rerouting metal line is selectively provide to form an electrical pathway from at least one second metal line to the third metal line.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.